Electrical circuit suitable for decoding a binary data stream that has been encoded in a sequential bitcell code format, the encoding resulting in an encoded signal waveform that carries clock information and data information, which electrical circuit comprises: a) a separator means (i) for inputting the encoded signal waveform and separating the clock information from the data information, and (ii) for generating an output clock signal and an output data signal, for each of a succession of bitcells; b) a clock signal integrator for calculating the duration of the bit cell; c) a circuit integrator for determining the center of the bitcell; d) a comparer means for: (i) determining in which part of the bitcell is the data signal, (ii) assigning the decoded signal a first valuation if the data signal is in the first part of the bitcell, and a second valuation if the data signal is in the second part of the bitcell. This circuit preserves the self clocking, velocity insensitive features of the code format.