Digital filter used in a sigma-delta decoder wherein each input sample is involved in the computation of three consecutive PCM output samples. During one sigma-delta sampling period, the filter performs three parallel operations by multiplexing (44) one adder (36) running three times faster than the sigma-delta clock for loading one of three accumulators (38, 40, 42). As the analog-to-digital converter must be kept in phase with remote modem transmit clock, the PCM sampling clock is controlled by the phase tracking performed by adding or subtracting one period of the crystal oscillator from time to time to the PCM sampling clock period. Rotating the order the accumulators are loaded by the adder each PCM sampling time enables to have zero as last coefficient value to add to the accumulator the contents of which is used as PCM output samples. Thus, each PCM sample value is available in the corresponding accumulator one sigma-delta clock period before the last computation. In case of a correction which shortens or lengthens the PCM sampling period, this correction does not change the PCM sample value to be output since the last computation which is either cancelled or repeated, consists in adding zero to the previous accumulator contents.