The described parallel processing apparatus and method turns a processing state discrimination flag (PE, 116) off, increases a program count by 1 at a time, reads out one instruction, and processes that instruction in an arithmetic unit, when it executes successivc processing of conventional software, and when it executes parallel processing of new software turns the processing state discrimination flag (PE, 116) on, increases the program count by m at a time, reads out m instructions, and exercises parallel processing over m instructions in m arithmetic units. In order to select either of the above described two kinds of processing, a discrimination changeover instruction having function of changing over the processing state discrimination flag (PE, 116) is added. The instructions are processed in one or in m arithmetic unit(s) (108, 109) in accordance with the processing state discrimination flag. In this way, successive processing and parallel processing are provided with compatibility and are selectively executed.