发明公开
EP0438800A2 Neural network processing system using semiconductor memories
失效
Halbleiterspeicher benutzendes神经元Netzwerk。
- 专利标题: Neural network processing system using semiconductor memories
- 专利标题(中): Halbleiterspeicher benutzendes神经元Netzwerk。
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申请号: EP90125680.0申请日: 1990-12-28
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公开(公告)号: EP0438800A2公开(公告)日: 1991-07-31
- 发明人: Watanabe, Takao , Kimura, Katsutaka , Itoh, Kiyoo , Kawajiri, Yoshiki
- 申请人: HITACHI, LTD.
- 申请人地址: 6, Kanda Surugadai 4-chome Chiyoda-ku, Tokyo 101 JP
- 专利权人: HITACHI, LTD.
- 当前专利权人: HITACHI, LTD.
- 当前专利权人地址: 6, Kanda Surugadai 4-chome Chiyoda-ku, Tokyo 101 JP
- 代理机构: Strehl Schübel-Hopf Groening & Partner
- 优先权: JP12538/90 19900124; JP119828/90 19900511
- 主分类号: G06F13/00
- IPC分类号: G06F13/00 ; G06F15/80
摘要:
Herein disclosed is a data processing system having a memory packaged therein for realizing a large-scale and high-speed parallel distributed processing and, especially, a data processing system for the neural network processing. The neural network processing system according to the present invention comprises: a memory circuit for storing neuron output values, connection weights, the desired values of outputs, and data necessary for learning; an input/output circuit for writing or reading data in or out of said memory circuit; a processing circuit for performing a processing for determining the neuron outputs such as the product, sum and nonlinear conversion of the data stored in said memory circuit, a comparison of the output value and its desired value, and a processing necessary for learning; and a control circuit for controlling the operations of said memory circuit, said input/output circuit and said processing circuit. The processing circuit is constructed to include at least one of an adder, a multiplier, a nonlinear transfer function circuit and a comparator so that at least a portion of the processing necessary for determining the neutron output values such as the product or sum may be accomplished in parallel. Moreover, these circuits are shared among a plurality of neutrons and are operated in a time sharing manner to determine the plural neuron output values. Still moreover, the aforementioned comparator compares the neuron output value determined and the desired value of the output in parallel.
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