发明公开
EP0458362A2 Low power consumption programmable logic array (PLA) and data processing system incorporating the PLA
失效
可编程逻辑阵列（PLA），低功耗和数据处理系统与此PLA。
- 专利标题： Low power consumption programmable logic array (PLA) and data processing system incorporating the PLA
- 专利标题（中）： 可编程逻辑阵列（PLA），低功耗和数据处理系统与此PLA。
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申请号： EP91108485.3申请日： 1991-05-24
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公开(公告)号： EP0458362A2公开(公告)日： 1991-11-27
- 发明人: Horie, Atsushi , Utsumi, Tohru
- 申请人： KABUSHIKI KAISHA TOSHIBA
- 申请人地址： 72, Horikawa-cho, Saiwai-ku Kawasaki-shi, Kanagawa-ken 210 JP
- 专利权人： KABUSHIKI KAISHA TOSHIBA
- 当前专利权人： KABUSHIKI KAISHA TOSHIBA
- 当前专利权人地址： 72, Horikawa-cho, Saiwai-ku Kawasaki-shi, Kanagawa-ken 210 JP
- 代理机构： Lehn, Werner, Dipl.-Ing.
- 优先权： JP132498/90 19900524; JP97579/91 19910426
- 主分类号： H03K19/177
- IPC分类号： H03K19/177 ; H03K19/00 ; G06F9/22
摘要：
Disclosed is a programmable logic array (PLA), comprising an AND plane comprising a plurality of input lines (10) and a plurality of product term lines (11) crossing the input lines (10), an OR plane comprising the product term lines (11) and a plurality of output lines (12) crossing the product term lines (11), a power source VDD providing an electrical power to the AND and OR planes, and control line for controlling the supply of the electric power to the AND and OR planes, wherein the electrical power from the power source VDD is provided to the PLA when a signal indicating the use of the PLA is provided to the control line, and the supply of the electrical power from the power source VDD to the PLA is stopped on receipt of a signal designating that the PLA is in the unused state. In addition, various data processing systems incorporating the PLA are disclosed.
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