A video signal processing circuit is provided to display an image of a standard television signal on a display unit with a 16:9 aspect ratio by enlarging an image of a video signal in the horizontal and vertical directions by a magnification factor which depends on the feature of the standard television signal. The processing circuit includes a first memory circuit (104) which reads out the stored video signal in response to a read clock different from the write clock and generated by a stable frequency source so that the image of the video signal is expanded in the vertical direction, a second memory circuit (105) which implements time-base compression for the output of the first memory circuit and thereafter expands the signal, a spatial filter (106) which implements filtering for the output of the second memory circuit, an enlargement control circuit (107) which control the above-mentioned circuits, and a synchronizing processing circuit (108). The circuit arrangement enables video signals of various image sizes, such as for movie pictures, to be displayed by signal conversion on a display unit with a 16:9 aspect ratio, and is capable of suppressing jitters of video signals.