发明公开
EP0536943A2 Data security arrangements for semiconductor programmable logic devices
失效
Datensicherheitseinrichtungenfürprogrammierbare logische Halbleiterschaltungen。
- 专利标题： Data security arrangements for semiconductor programmable logic devices
- 专利标题（中）： Datensicherheitseinrichtungenfürprogrammierbare logische Halbleiterschaltungen。
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申请号： EP92308939.5申请日： 1992-09-30
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公开(公告)号： EP0536943A2公开(公告)日： 1993-04-14
- 发明人: Austin, Kenneth
- 申请人： Pilkington Micro-Electronics Limited
- 申请人地址： Prescot Road St. Helens Merseyside WA10 3TT GB
- 专利权人： Pilkington Micro-Electronics Limited
- 当前专利权人： Pilkington Micro-Electronics Limited
- 当前专利权人地址： Prescot Road St. Helens Merseyside WA10 3TT GB
- 代理机构： Palmer, Roger
- 优先权： GB9121591 19911011
- 主分类号： G06F12/14
- IPC分类号： G06F12/14
摘要：
A data security arrangement is provided to protect configuration data to be stored in static random access memories (38) in semiconductor programmable logic devices PLD. The configuration data, which is vulnerable to illegal duplication, is normally held in a read only memory ROM, typically an erasable programmable read only memory.
A data coding means is provided to code the configuration data to be loaded to the PLD and a data decoding means is provided in the PLD to decode the coded configuration data. The coding and decoding means each incorporate maximal length shift registers (12, 25) which generate a pseudo-random sequence of bits. A key value is input to the shift register (12) in the coding means forcing it to start at a particular point in the sequence. The output (bits B28 and B31) of this register is combined in an EXCLUSIVE-OR gate (20) with configuration data and coded data is written to the read only memory ROM (24). The decoding means in the PLD has a corresponding key value held in a non-volatile memory (28) in the PLD. This is applied to the register (25) of the decoding means whose output (bits B28 and B31) are combined in an EXCLUSIVE-OR GATE (34) with coded configuration data CDIC read from the ROM (24) to produce decoded configuration data CDOD to be sotred in the memories (38).
A data coding means is provided to code the configuration data to be loaded to the PLD and a data decoding means is provided in the PLD to decode the coded configuration data. The coding and decoding means each incorporate maximal length shift registers (12, 25) which generate a pseudo-random sequence of bits. A key value is input to the shift register (12) in the coding means forcing it to start at a particular point in the sequence. The output (bits B28 and B31) of this register is combined in an EXCLUSIVE-OR gate (20) with configuration data and coded data is written to the read only memory ROM (24). The decoding means in the PLD has a corresponding key value held in a non-volatile memory (28) in the PLD. This is applied to the register (25) of the decoding means whose output (bits B28 and B31) are combined in an EXCLUSIVE-OR GATE (34) with coded configuration data CDIC read from the ROM (24) to produce decoded configuration data CDOD to be sotred in the memories (38).
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