发明公开
EP0571683A1 High performance data re-alignment mechanism with multiple buffers in a memory access control device 失效
机构具有大容量与在存储器访问控制设备中的多个缓冲器中的数据重新排列。

High performance data re-alignment mechanism with multiple buffers in a memory access control device
摘要:
The data re-alignment method and device to be used in the transmission of data from a plurality of source buffers (113) of the shared memory to a flip-flop target buffers (117) before they are transferred to different users that share the memory, each source buffer being organized in 2 n byte words and the target buffer being organized in 2 m byte words, where m is greater than n.
To perform a memory read operation, the data read from different source buffers are transferred to a Buffer Interface Register (122) for the re-alignment to match the size of the bytes word of the target buffer. Therefore, after successive reading from the source buffer to write the data into the BIR, the BIR which houses (2 m + 2 n - 1) bytes may loop back the exceeding bytes which are from position (2 m + 1) to (2 m + 2 n - 1) to which are added the next 2 n bytes read from the source buffer while the first 2 m bytes are transferred to the target buffer (117). The mechanism enables to avoid useless steps during the reading, the writing and the transfer.
A pointer management system is adapted to the method and the device of the present invention in order to manage the data byte content of each word of the source buffers by indicating its beginning and its ending, and to manage the BIR to enable to loop the exceeding bytes to the first position of the BIR to which are added the next bytes from the source buffer, while the first eight bytes are transferred to the target buffer (117).
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