Providing low-skew clock signals to a Field Programmable Gate Array (FPGA) chip normally requires devoting a certain number of bondpads to that purpose. However, that limits the number of clocks that may be applied, and may also limit which bondpads can be used for that purpose. In the present invention, any input/output bondpad (eg., 238 - 241; 246 - 249) may be used to supply a low-skew clock, or other global type signal, to one or more of the Programmable Function Units (PFUs) (eg., 205 - 213). This is accomplished by using a criss-crossed grid of parallel conductor groups (eg., 254, 255). Any of the conductors may be supplied by a clock from a bondpad or alternatively driven directly from a PFU, thereby allowing the distribution of internally-generated clocks. To facilitate programmable interconnects between the horizontal and vertical conductors, the outer conductor in a group crosses over the others at defined intervals, to thereby become the inner conductor. In this manner, each cell (eg., 201 - 204) may drive a subset of the conductors in a group, thereby reducing the number of drivers needed. This allows all the buffer and conductor topologies to be identical for each cell, which significantly aids in the computer-aided design of the FPGA, as well as simplifying its programming.