A field programmable gate array includes a dedicated path (606) which directly connects an I/O pad (604) to a selected register (603) in the array of programmable function units (602). For example, a direct connection (i.e., without a configurable interconnect point) is provided from an I/O pad, through an input driver (605), to the input of a selected register in a given PFU. Either this same path, or alternatively a different path, may also be used to directly connect a register output from a given PFU to an I/O pad, through an output driver. This technique avoids the need for special I/O registers in the programmable input/output cells, thereby increasing the flexibility of use and ease of design of the FPGA.