发明公开
EP0620600A2 Split-gate flash EEPROM cell and array with low voltage erasure
失效
闪存EEPROM - Zelle und Matrix mit geteiltem Gate和schwacher Loschspannung。
- 专利标题： Split-gate flash EEPROM cell and array with low voltage erasure
- 专利标题（中）： 闪存EEPROM - Zelle und Matrix mit geteiltem Gate和schwacher Loschspannung。
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申请号： EP94302670.8申请日： 1994-04-14
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公开(公告)号： EP0620600A2公开(公告)日： 1994-10-19
- 发明人: Chang, Chen-Chi P. , Li, Mei F.
- 申请人： Hughes Aircraft Company
- 申请人地址： 7200 Hughes Terrace, P.O. Box 80028 Los Angeles, California 90080-0028 US
- 专利权人： Hughes Aircraft Company
- 当前专利权人： Hughes Aircraft Company
- 当前专利权人地址： 7200 Hughes Terrace, P.O. Box 80028 Los Angeles, California 90080-0028 US
- 代理机构： Colgan, Stephen James
- 优先权： US47134 19930416
- 主分类号： H01L29/788
- IPC分类号： H01L29/788 ; H01L27/115 ; G11C16/04 ; H01L29/60
摘要：
Each unit cell (10) of a flash EEPROM array (50) includes a control gate (38) having a section (38b) disposed in series between a program section (34a) of a floating gate (34) and a source (18) to provide threshold voltage control for erasure. The floating gate (34) further has an erase section (34b) which extends from the program section (34a) around an end of a channel (22) to the source (18). A thin tunnel oxide layer (32) is formed between an end portion (34c) of the erase section (34b) and an underlying portion of the source (18) which enables the floating gate (34) to be erased by Fowler-Nordheim tunneling from the end portion (34c) through the oxide layer (32) to the source (18) with low applied voltages.
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