An adaptive clock recovery arrangement for deriving a synchronous clock from an asynchronous, packet stream (11) such as an asynchronous transfer mode (ATM) cell stream. The deviation in the magnitude of information stored in a first-in-first-out memory (15) is continually monitored (25), and the synchronous clock frequency, referred to as the adaptive line clock frequency, is adjusted in a plurality of modes, under the control of a processor (29). The adjustment is made in response to a detected increasing condition of the monitored deviation. The adjustments are open-loop adjustments made without continually adjusting the adaptive line clock frequency based on the monitored deviation. Damping is substantially reduced compared with "conventional" PLL arrangements because the open-loop adjustments result in a rapid frequency correction with perfect or nearly perfect deadbeat damping, i.e. without the frequency oscillations that continue after the correct frequency is reached in closed-loop arrangements.