A data processor comprises a bus control circuit (14) adapted to be interfaced with a synchronous DRAM (22) which can be accessed in synchronism with a clock signal (CLK), a plurality of data processing modules (12, 13) coupled to said bus control circuit (14) for producing data and addresses for accessing a memory (22), and a clock driver (16) for feeding intrinsic operation clocks to said data processing modules (12, 13) and for feeding the clock signal for accessing said memory (22) in synchronism with the operations of said data processing modules (12, 13) to be operated by the operation clock signals, to the outside.