发明公开
EP0675543A2 Semiconductor device including protection means and manufacturing method thereof
失效
Halbleiterbauelement mit einem Schutzmittel und Herstellungsverfahren。
- 专利标题： Semiconductor device including protection means and manufacturing method thereof
- 专利标题（中）： Halbleiterbauelement mit einem Schutzmittel und Herstellungsverfahren。
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申请号： EP95302171.4申请日： 1995-03-31
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公开(公告)号： EP0675543A2公开(公告)日： 1995-10-04
- 发明人: Saitoh, Yutaka, c/o Seiko Instruments Inc. , Osanai, Jun, c/o Seiko Instruments Inc.
- 申请人： SEIKO INSTRUMENTS INC.
- 申请人地址： 8 Nakase 1-chome, Mihama-ku Chiba-shi, Chiba 261 JP
- 专利权人： SEIKO INSTRUMENTS INC.
- 当前专利权人： SEIKO INSTRUMENTS INC.
- 当前专利权人地址： 8 Nakase 1-chome, Mihama-ku Chiba-shi, Chiba 261 JP
- 代理机构： Sturt, Clifford Mark
- 优先权： JP63780/94 19940331; JP56140/95 19950315
- 主分类号： H01L27/02
- IPC分类号： H01L27/02
摘要：
An improvement of a resistance to electrostatic discharge of a semiconductor integrated circuit device is provided. An IC having a high ESD immunity is realised by causing a surface concentration of N type impurities in a drain area (409) of an N-channel type MOS transistor to be more than 5 E 18/cm 3 and in the direction of a source area (401) to have a monotonously decreasing concentration profile in which there is no kink in a portion less than 5 E 18/cm 3 in the surface region under a gate electrode (410).
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