The digital processing apparatus (P1) includes a high speed response PLL (13) that produces a first clock signal (Sc1) locked on the horizontal synchronization signal (H. sync.) included in the video signal (Sv) input thereto. A analog to digital converter (19) converts the input video signal (Sv) with respect to the first clock signal (Sc1) into a digitized video signal (Svc). A write controller (7) controls a video memory (6) to store the digitized video signal (Svc) based on the first clock signal (Sc1). A low speed response PLL (15) produces a second clock signal (Sc2) based on the vertical synchronization signal (V. sync.) included in the video signal (Sv). A read controller (8) controls the video memory (6) to read out the stored digitized video signal (Svc) therefrom based on the second control signal (Sc2). In thus constructed digital processing apparatus (P1) can store and read the digitized video signal (Svc) to and from the video memory (6) stably, enabling to process the video signal (Svc) read out from the video memory (6) effectively and securely.