In a variable delay circuit comprising a high-speed clock generator (100) receiving a trigger signal (10a) and outputting a pulse signal after a desired time interval from rising of the trigger signal (10a) and a coarse delay signal generator (500), the high-speed clock generator (100) comprises a rising edge detector (11) receiving the trigger signal (10a), detecting a rising edge of the trigger signal (10a), and outputting an edge detecting pulse (11a) having a time interval, and an asynchronous reset oscillator (12) receiving the edge detecting pulse (11a), being reset at rising of the edge detecting pulse (11a), and starting to generate a high-speed clock (12a) at falling of the edge detecting pulse (11a). Therefore, the high-speed clock generator (100) for the variable delay circuit is realized without using analog circuits. Further, since the high-speed clock generator (100) includes no PLL, it is not necessary to provide analog circuits, such as charge pump and VCO, on a digital LSI and, therefore, special considerations for the analog circuits are dispensed with.