A P-channel MOS memory cell has P+ source (14) and drain (16) regions formed in an N-well (18). A thin tunnel oxide (24) is provided between the well surface and an overlying floating gate (22). In one embodiment, the thin tunnel oxide (24) extends over a substantial portion of the active region (12) of the device. An overlying control gate (26) is insulated from the floating gate (22) by an insulating layer (28). The device is programmed via hot electron injection from the drain end of the channel region (12) to the floating gate (22), without avalanche breakdown, which allows the cell to be bit-selectable during programming. Erasing is accomplished by electron tunneling from the floating gate (22) to the N-well (18) with the source (14), drain (16), and N-well (18) regions equally biased. Since there is no high drain/well junction bias voltage, the channel length of the cell may be reduced without incurring and destructive junction stress.