Multiplication is performed including accumulation at high speed by a small quantity of hardware. Analog voltage X i corresponding to each clement of the first input data string is input to capacitance switching circuits 10 1 to 10 n through input terminals 1 1 to 1 n . m bit of digital control data A i corresponding to each element of the second input data string are input to each capacitance switching circuit 10 i , and each bit a j of the control signal A j is input to the corresponding multiplexer circuit 6 ij . In the multiplexer circuit 6 ij , the capacitances C ij corresponding to the value of each bit of the control signal a j are connected to the input terminal 1 i or the reference charge V STD . The voltages corresponding to the products of inputted analog voltages X i and the control signals A i are outputted from each capacitance switching circuit 10 i . The output voltages of each capacitance switching circuit 10 i are parallelly inputted to the operational amplifier 3 connected by a feedback capacitance Cf, and the sum of the input voltages is outputted from the operational amplifier 3. On the other hand, in order to provide a multiplication circuit of high calculation speed without deteriorating the calculation accuracy and circuit density, a multiplication circuit according to the present invention has a MOS switch or MOS multiplexer the MOS of which has a gate with width and length so that a time constant defined by the input capacitance and the switch etc. is constant.