发明公开
EP0804803A1 BARRIER ENHANCEMENT AT THE SIALICIDE LAYER 失效
BARRIER增加自对准硅化物层

  • 专利标题: BARRIER ENHANCEMENT AT THE SIALICIDE LAYER
  • 专利标题(中): BARRIER增加自对准硅化物层
  • 申请号: EP94929856.0
    申请日: 1994-09-22
  • 公开(公告)号: EP0804803A1
    公开(公告)日: 1997-11-05
  • 发明人: BRUGGE, Hunter, B.
  • 申请人: VLSI TECHNOLOGY, INC.
  • 申请人地址: 1109 McKay Drive San Jose California 95131 US
  • 专利权人: VLSI TECHNOLOGY, INC.
  • 当前专利权人: VLSI TECHNOLOGY, INC.
  • 当前专利权人地址: 1109 McKay Drive San Jose California 95131 US
  • 代理机构: Kahler, Kurt, Dipl.-Ing.
  • 优先权: US19930126353 19930924
  • 国际公布: WO1995008839 19950330
  • 主分类号: H01L21
  • IPC分类号: H01L21 H01L23
BARRIER ENHANCEMENT AT THE SIALICIDE LAYER
摘要:
A first metallic layer (16) is deposited over the substrate (10) and the contact well (14) formed therein. The first metallic layer (16) is then exposed to a gas to allow the gas to stuff the first metallic layer, thereby improving the barrier characteristics of the first metallic layer. A second metallic layer (22) is deposited over the first stuffed metallic layer (16). A third metallic layer (24) is then deposited over the second metallic layer. An anti-reflective fourth layer of metal (26) is then deposited over the third metallic layer (24). The exposure of the first metallic layer (16) to a gas and all of the metal layer deposition steps are performed in a low-pressure environment. Also, as an result of subsequent processing steps required in the formation of semiconductor devices, the portions of the first metallic layer which are present outside of the contact well are removed. The remaining portion of the first metallic layer forms a self-aligned silicide within the contact well.
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