发明公开
EP0810517A2 Hardware mechanism for optimizing instruction and data prefetching
失效
五金 - Anordnung zur optimierten Vorausholung von Befehlen和Daten
- 专利标题: Hardware mechanism for optimizing instruction and data prefetching
- 专利标题(中): 五金 - Anordnung zur optimierten Vorausholung von Befehlen和Daten
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申请号: EP97107455.4申请日: 1997-05-06
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公开(公告)号: EP0810517A2公开(公告)日: 1997-12-03
- 发明人: Emberson, David R.
- 申请人: SUN MICROSYSTEMS, INC.
- 申请人地址: 2550 Garcia Avenue Mountain View, CA 94043 US
- 专利权人: SUN MICROSYSTEMS, INC.
- 当前专利权人: SUN MICROSYSTEMS, INC.
- 当前专利权人地址: 2550 Garcia Avenue Mountain View, CA 94043 US
- 代理机构: Zangs, Rainer E., Dipl.-Ing.
- 优先权: US648533 19960515
- 主分类号: G06F9/38
- IPC分类号: G06F9/38 ; G06F12/08
摘要:
Disclosed is a prefetch execution unit, prefetch instruction buffer and a prefetch victim buffer which operate to optimize prefetching by recording a particular cache miss' history. To record cache misses, victimized (overwritten) lines and/or a prefetch tag are stored in a prefetch victim buffer. When the processor experiences a cache miss, it accesses the prefetch victim buffer to retrieve information relating to the prefetch victim. The prefetch execution unit then modifies the values of the additional field or fields and then stores the modified augmented prefetch instruction in the prefetch instruction buffer. The next time a prefetch instruction for the victimized lines is executed by the processor, the new values of the modified augmented prefetch instruction will dictate where the prefetch information is stored or what size increment it has. By continuous modification of the augmented prefetch instructions, eventually thrashing may be eliminated.
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