发明公开
EP0836229A3 Method and structure for integration of passive components on flexible film layers
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方法及结构上的柔性薄膜层的无源元件的集成
- 专利标题: Method and structure for integration of passive components on flexible film layers
- 专利标题(中): 方法及结构上的柔性薄膜层的无源元件的集成
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申请号: EP97305828.2申请日: 1997-08-01
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公开(公告)号: EP0836229A3公开(公告)日: 1999-06-02
- 发明人: Saia, Richard Joseph , Durocher, Kevin Matthew , Cole, Herbert Stanley
- 申请人: GENERAL ELECTRIC COMPANY
- 申请人地址: 1 River Road Schenectady, NY 12345 US
- 专利权人: GENERAL ELECTRIC COMPANY
- 当前专利权人: GENERAL ELECTRIC COMPANY
- 当前专利权人地址: 1 River Road Schenectady, NY 12345 US
- 代理机构: Goode, Ian Roy
- 优先权: US731172 19961010
- 主分类号: H01L23/538
- IPC分类号: H01L23/538 ; H01L25/16
摘要:
A method for fabricating a flexible interconnect film includes applying a resistor layer (16,18) over one or both surfaces of a dielectric film (10); applying a metallization layer (22) over the resistor layer with the resistor layer including a material facilitating adhesion of the dielectric film and the metallization layer; applying a capacitor dielectric layer (24a) over the metallization layer; and applying a capacitor electrode layer (26a) over the capacitor dielectric layer. The capacitor electrode layer is patterned to form a first capacitor electrode; the capacitor dielectric layer is patterned; the metallization layer is patterned to form a resistor (28); and the metallization layer and the resistor layer are patterned to form an inductor (33) and a second capacitor electrode. In one embodiment, the dielectric film includes a polyimide, the resistor layer includes tantalum nitride, and the capacitor dielectric layer includes amorphous hydrogenated carbon or tantalum oxide. If the resistor and metallization layers are applied over both surfaces of the dielectric film, passive components can be fabricated on both surfaces of the dielectric film. The dielectric film can have vias therein with the resistor and metallization layers extending through the vias. A circuit chip can be attached and coupled to the passive components by metallization patterned through vias in an additional dielectric layer.
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