发明公开
- 专利标题: Bit line configuration for DRAM
- 专利标题(中): BitleitungsanordnungfürDRAM
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申请号: EP98305124.4申请日: 1998-06-29
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公开(公告)号: EP0889528A2公开(公告)日: 1999-01-07
- 发明人: Hoenigschmid, Heinz , DeBrosse, John
- 申请人: SIEMENS AKTIENGESELLSCHAFT , International Business Machines Corporation
- 申请人地址: Wittelsbacherplatz 2 80333 München DE
- 专利权人: SIEMENS AKTIENGESELLSCHAFT,International Business Machines Corporation
- 当前专利权人: SIEMENS AKTIENGESELLSCHAFT,International Business Machines Corporation
- 当前专利权人地址: Wittelsbacherplatz 2 80333 München DE
- 代理机构: Litchfield, Laura Marie
- 优先权: US884853 19970630
- 主分类号: H01L27/108
- IPC分类号: H01L27/108
摘要:
A dynamic random access memory array having an array of memory cells. Individual cells of the array are addressable by a plurality of word lines and a plurality of bit lines. The memory cells are disposed in active areas of the array. The array of memory cells includes a first strip of memory cells. The dynamic random access memory array includes a lower metal layer and an upper metal layer disposed above the lower metal layer. The dynamic random access memory array further includes a dielectric layer disposed between the lower metal layer and the upper metal layer. There is further included a first bit line of the plurality of bit lines which includes a lower metal first bit line portion implemented in the lower metal layer. The lower metal first bit line portion is coupled to a first plurality of memory cells of the first strip of memory cells. The first bit line also includes an upper metal first bit line portion implemented in the upper metal layer. The upper metal first bit line portion is coupled to the lower first metal bit line portion by a first contact through the dielectric layer. The first contact is disposed above one of the active areas.
公开/授权文献
- EP0889528B1 Bit line configuration for DRAM 公开/授权日:2010-08-18
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