发明公开
EP0889528A2 Bit line configuration for DRAM 失效
BitleitungsanordnungfürDRAM

Bit line configuration for DRAM
摘要:
A dynamic random access memory array having an array of memory cells. Individual cells of the array are addressable by a plurality of word lines and a plurality of bit lines. The memory cells are disposed in active areas of the array. The array of memory cells includes a first strip of memory cells. The dynamic random access memory array includes a lower metal layer and an upper metal layer disposed above the lower metal layer. The dynamic random access memory array further includes a dielectric layer disposed between the lower metal layer and the upper metal layer. There is further included a first bit line of the plurality of bit lines which includes a lower metal first bit line portion implemented in the lower metal layer. The lower metal first bit line portion is coupled to a first plurality of memory cells of the first strip of memory cells. The first bit line also includes an upper metal first bit line portion implemented in the upper metal layer. The upper metal first bit line portion is coupled to the lower first metal bit line portion by a first contact through the dielectric layer. The first contact is disposed above one of the active areas.
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