An apparatus for connecting a bus to a RAM comprising :

a single address generator providing complete addresses that is clocked at a first clock rate;
a RAM interface, comprising :

a plurality of swing buffers connected to a bus for receiving therefrom a plurality of data words from a source at a second clock rate ;
a control coupled to said swing buffers
a two-wire link connecting said control with said address generator wherein a request/acknowledge protocol is implemented therebetween via said link, wherein said two-wire link comprises a sender, a receiver, and a clock connected to said sender and said receiver, wherein data is transferred from said sender to said receiver upon a transition of said clock only when said sender is ready and said receiver is ready;
wherein the interface is clocked at a third clock rate that is asynchronous with said first clock rate and said second clock rate, and data is transferred between a selected swing buffer and a RAM in response to a first signal that is generated by said control when said control receives an address from the address generator and said control receives a second signal from said selected swing buffer via said communication link