发明公开
- 专利标题: Division circuit and method
- 专利标题(中): Dividierschaltung und -verfahren
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申请号: EP98120014.0申请日: 1992-06-22
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公开(公告)号: EP0902358A2公开(公告)日: 1999-03-17
- 发明人: Kawasaki, Shumpei , Sakakibara, Eiji , Fukada, Kaoru , Yamazaki, Takanaga , Akao, Yasushi , Baba, Shiro , Kihara, Toshimasa , Kurakazu, Keiichi , Tsukamoto, Takashi , Masumura, Shigeki , Tawara, Yasuhiro , Kashiwagi, Yugo , Fujita, Shuya , Ishida, Katsuhiko , Sawa, Noriko , Asano, Yoichi , Chaki, Hideaki , Sugawara, Tadahiko , Kainaga, Masahiro , Noguchi, Kouki B-11, Hitachitennouueshataku , Watabe, Mitsuru
- 申请人: Hitachi, Ltd. , HITACHI ULSI ENGINEERING CORPORATION , HITACHI MICROCOMPUTER SYSTEM LTD.
- 申请人地址: 6 Kanda Surugadai 4-chome Chiyoda-ku, Tokyo 101-8010 JP
- 专利权人: Hitachi, Ltd.,HITACHI ULSI ENGINEERING CORPORATION,HITACHI MICROCOMPUTER SYSTEM LTD.
- 当前专利权人: Hitachi, Ltd.,HITACHI ULSI ENGINEERING CORPORATION,HITACHI MICROCOMPUTER SYSTEM LTD.
- 当前专利权人地址: 6 Kanda Surugadai 4-chome Chiyoda-ku, Tokyo 101-8010 JP
- 代理机构: Strehl Schübel-Hopf & Partner
- 优先权: JP178739/91 19910624; JP154525/92 19920521
- 主分类号: G06F7/52
- IPC分类号: G06F7/52
摘要:
A microcomputer MCU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting an instruction format of a fixed length of 2 n bits which is smaller than the length of the maximum data word fed to instruction execution means. The control of the coded division is executed by noting the code bits.
公开/授权文献
- EP0902358A3 Division circuit and method 公开/授权日:2002-01-02
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