发明公开
EP0903803A3 Power splitter/combiner circuit, high power amplifier and balun circuit
有权
Leistungsteilungs - / - addierschaltung,Hochleistungsverstärkerund Symmetrierschaltung
- 专利标题: Power splitter/combiner circuit, high power amplifier and balun circuit
- 专利标题(中): Leistungsteilungs - / - addierschaltung,Hochleistungsverstärkerund Symmetrierschaltung
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申请号: EP98117393.3申请日: 1998-09-14
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公开(公告)号: EP0903803A3公开(公告)日: 2001-05-30
- 发明人: Ishida, Kaoru , Miyaji, Masayuki , Kosugi, Hiroaki , Kugou, Shin'ichi
- 申请人: Matsushita Electric Industrial Co., Ltd.
- 申请人地址: 1006, Oaza-Kadoma Kadoma-shi, Osaka 571-8501 JP
- 专利权人: Matsushita Electric Industrial Co., Ltd.
- 当前专利权人: Matsushita Electric Industrial Co., Ltd.
- 当前专利权人地址: 1006, Oaza-Kadoma Kadoma-shi, Osaka 571-8501 JP
- 代理机构: Grünecker, Kinkeldey, Stockmair & Schwanhäusser Anwaltssozietät
- 优先权: JP25241797 19970917; JP25241997 19970917
- 主分类号: H01P5/10
- IPC分类号: H01P5/10 ; H01P5/12 ; H03F3/60
摘要:
A high power amplifier has a first balun propagating a half of an input signal to an in-phase output terminal, and also propagating a fourth of the input signal to first and second opposite-phase output terminals, the signal propagated to the first and second opposite-phase output terminals lagging 180 degrees behind the signal propagated to the in-phase output terminal; first and second power amplifier circuits connected to the first and second opposite-phase output terminals of the first balun and having the same characteristics;a third power amplifier circuit connected to the in-phase output terminal of the first balun and having output power substantially twice as much as the output power of the first or second power amplifier circuit; and a second balun having first and second opposite-phase input terminals for receiving the outputs of the first and second power amplifier circuits, having an in-phase input terminal for receiving the output of the third power amplifier circuit, combining the outputs of the first, second and third power amplifier circuits, and propagating combined output.
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