Disclosed is a high density semiconductor memory having diagonal bit lines and a dual word line configuration with highly efficient use of chip area. In an exemplary embodiment, the semiconductor memory includes a memory cell array (10) of memory cells arranged in rows and columns, and a plurality of diagonal bit lines (BLP 1 -BLP N ) arranged in a pattern that changes horizontal direction along the memory cell array to facilitate access to said memory cells. True bit lines are periodically twisted at locations (33) in the vertical plane with the associated complementary bit lines. The bit lines are arranged non-orthogonal to a plurality of dual word lines (WL 1 -WL M ), where each dual word line includes a master word line (MWL i ) at a first layer and a plurality of local word lines (LWL 1 -LWL X ) at a second layer. The local word lines are connected to the master word line of a common row via a plurality of spaced electrical connections (29), e.g., electrical contacts in a "stitched" architecture, and each local word line is connected to plural memory cells (MC). The electrical contacts or stitches (29) that connect the local word lines to the associated master word line follow the same zigzag pattern in the horizontal plane as the bit it lines. Accordingly, the area penalty of the segmented architecture of FIG. 1A is largely eliminated.