The present invention relates to a semiconductor memory device capable of performing a write operation 1 or 2 cycles after receiving a write command without necessitating a dead cycle. The elimination of the dead cycle between read and write operations improves bus efficiency and thus, speed. The memory device of the present invention includes an address input control means for receiving an external write or read address and delaying the write address by 1 cycle when the memory device operates in a write after 1 cycle mode or by 2 cycles when the memory device operates in a write after 2 cycles mode. A data input control means receives external write data and delaying the write data by a first predetermined number of cycles when the memory device operates in the write after 1 cycle mode or delaying the write data by a second predetermined number of cycles when the memory device operates in the write after 2 cycles mode. A data transmission control means transmits the delayed write data responsive to a predetermined set of input commands. The data input control means reads the data from a cell corresponding to the read address, provides the write data to a cell corresponding to the write address using a flow through method in the write after 1 cycle mode and using a pipeline method in the write after 2 cycles mode, and writes the transmitted delayed data into the cell corresponding to the write address. The first predetermined number of cycles is either 0 or 1 and the second predetermined number of cycles are 0, 1, or 2. The data transmission control means transmits write data delayed by 0 cycles when a write, write command sequence is received in the write after 1 cycle mode, transmits write data delayed by 1 cycle when a read, write command sequence is received in the write after 1 cycle mode, transmits write data delayed by 0 cycles when a write, write, write command sequence is received in the write after 2 cycles mode, transmits write data delayed by 1 cycle when either a write, read, write or a read, write, write command sequence is received in the write after 2 cycles mode, and transmits write data delayed by 2 cycles when a read, read, write command sequence is received in the write after 2 cycles mode.