发明公开
- 专利标题: Correlator method and apparatus
- 专利标题(中): Korrelationsverfahren undGerät
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申请号: EP00103906.4申请日: 2000-02-24
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公开(公告)号: EP1033661A2公开(公告)日: 2000-09-06
- 发明人: Iizuka, Kunihiko , Senderowicz, Daniel, c/o Synchro Design Inc.
- 申请人: SHARP KABUSHIKI KAISHA , SYNCHRO DESIGN Inc.
- 申请人地址: 22-22 Nagaike-cho Abeno-ku Osaka 545-8522 JP
- 专利权人: SHARP KABUSHIKI KAISHA,SYNCHRO DESIGN Inc.
- 当前专利权人: SHARP KABUSHIKI KAISHA,SYNCHRO DESIGN Inc.
- 当前专利权人地址: 22-22 Nagaike-cho Abeno-ku Osaka 545-8522 JP
- 代理机构: MÜLLER & HOFFMANN Patentanwälte
- 优先权: US259281 19990301; US499631 20000208
- 主分类号: G06F17/15
- IPC分类号: G06F17/15
摘要:
An analog input signal that is sampled at a predetermined rate is multiplied by a corresponding binary code sequence, i.e. "+1" or "-1" by the multiplier. The output of this multiplier is applied in conjunction with a signal supplied by the negative feed back circuit to the analog integrator. The quantization circuit quantizes the output signal of the analog integrator into N levels and outputs a digital word. This digital word is delayed by a unit time interval by a digital delay circuit and then processed by the above mentioned negative feed back circuit. As a result of this signal magnitude reducing process, the required integrating capacitance can be minimized without risks of saturation effects. Additionally, the output is already in digital form as required by the subsequent system blocks.
公开/授权文献
- EP1033661A3 Correlator method and apparatus 公开/授权日:2010-09-29
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