发明公开
EP1038227A1 A SYSTEM AND METHOD FOR TRAP ADDRESS MAPPING FOR FAULT ISOLATION
有权
2009秋季联合国少数群体宣言进程地址检测到系统故障隔离
- 专利标题: A SYSTEM AND METHOD FOR TRAP ADDRESS MAPPING FOR FAULT ISOLATION
- 专利标题(中): 2009秋季联合国少数群体宣言进程地址检测到系统故障隔离
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申请号: EP98957992.5申请日: 1998-11-16
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公开(公告)号: EP1038227A1公开(公告)日: 2000-09-27
- 发明人: ZIMMER, Vincent, J.
- 申请人: INTEL CORPORATION
- 申请人地址: 2200 Mission College Boulevard Santa Clara, CA 95052 US
- 专利权人: INTEL CORPORATION
- 当前专利权人: INTEL CORPORATION
- 当前专利权人地址: 2200 Mission College Boulevard Santa Clara, CA 95052 US
- 代理机构: Molyneaux, Martyn William
- 优先权: US989421 19971212
- 国际公布: WO9931591 19990624
- 主分类号: G06F12/00
- IPC分类号: G06F12/00 ; G06F11/00
摘要:
The invention relates to the alteration of a segment (230) and an offset (240) used to form an effective address (220) of the default interrupt handler routine. The method comprising a number of steps. First, a trap address (210) of a default interrupt handler routine is provided. This trap address includes a segment (230) and an offset (240) normally used to calculate the effective address (220) via conventional circuitry. However, a unique segment is produced by performing an arithmetic operation on the segment (230). Thereafter, another arithmetic operation is performed to produce a unique offset. These unique segment and offset values may still be used by the conventional circuitry to still produce the same effective addresses so that only one default interrupt handler routine is required. While this alteration produces a unique segment (230) and offset (240) which can be assigned to an interrupt, the segment and offset are modified appropriately to still use a common default interrupt handler.
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