A buffer circuit for providing dynamic threshold control. The buffer circuit includes a pair of input inverters (IV1,IV2) designed with different skewed threshold potential characteristics. The outputs of the skewed inverters (IV1,IV2) are directed to a logic circuit (30) designed to select either the faster or the slower signal received from the two inverters for transmission to passgate devices (40,50) coupled to the respective inverters. Only one of the passgate devices (40,50) is enabled to ensure that only one of the output signals from the two inverters is propagated through the buffer. A latch (60) is preferably connected between the logic circuit (30) and the two passgate devices (40,50) to maintain the states of the inverters (IV1,IV2) and the logic circuit (30). The circuit can be designed to define the threshold potential at which switching will occur so as to reduce propagation delay or increase it as desired. It is therefore possible using the circuit to increase transmission rates with minimal affect on signal noise.