Invention Publication
- Patent Title: Detector error suppresion circuit and method
- Patent Title (中): 检测器电路和方法，用于差错隐藏
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Application No.: EP00303986.4Application Date: 2000-05-11
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Publication No.: EP1054401A3Publication Date: 2001-09-05
- Inventor: Leung, Michael , Fu, Leo
- Applicant: Texas Instruments Incorporated
- Applicant Address: 7839 Churchill Way, Mail Station 3999 Dallas, Texas 75251 US
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: 7839 Churchill Way, Mail Station 3999 Dallas, Texas 75251 US
- Agency: Potter, Julian Mark
- Priority: US134909P 19990519
- Main IPC: G11B20/10
- IPC: G11B20/10 ; G11B20/18
Abstract:
Device and method of EEPR4 post processing in an EPR4 detection system to remove single bit errors by applying 1+D to the samples and comparing this to (1-D)(1+D) 3 to the detected EPR4 bits.
Public/Granted literature
- EP1054401B1 Detector error suppresion circuit and method Public/Granted day:2004-03-03
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