发明公开
EP1126617A3 Circuit and method for determing the phase difference between a sample clock and a sampled signal by linear approximation
审中-公开
装置和方法,用于确定与线性近似一个采样时钟和采样信号之间的相位差
- 专利标题: Circuit and method for determing the phase difference between a sample clock and a sampled signal by linear approximation
- 专利标题(中): 装置和方法,用于确定与线性近似一个采样时钟和采样信号之间的相位差
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申请号: EP01300806.5申请日: 2001-01-30
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公开(公告)号: EP1126617A3公开(公告)日: 2003-11-12
- 发明人: Ozdemir, Hakan
- 申请人: STMicroelectronics, Inc.
- 申请人地址: 1310 Electronics Drive Carrollton Texas 75006-5039 US
- 专利权人: STMicroelectronics, Inc.
- 当前专利权人: STMicroelectronics, Inc.
- 当前专利权人地址: 1310 Electronics Drive Carrollton Texas 75006-5039 US
- 代理机构: Palmer, Roger
- 优先权: US503929 20000214
- 主分类号: H03L7/091
- IPC分类号: H03L7/091 ; G11B20/14 ; G11B20/10
摘要:
A phase-calculation circuit (46) includes a buffer (42), an approximation circuit (70), and an interpolator (56). The buffer receives and stores first and second samples of a periodic signal having a peak amplitude. The approximation circuit (70) linearly approximates a portion of the periodic signal, and calculates the relative phase of one of the samples within the signal portion. The interpolator (56) calculates the absolute phase of that sample with respect to a predetermined point of the signal using the relative phase and the values of the first and second samples. The circuit is used to decrease the alignment-acquisition time of a digital timing-recovery loop, and allows a shortening of the preamble and a corresponding increase in the data-storage density of a disk. The circuit may determine an initial phase difference between a disk-drive read signal and a read-signal sample clock. The digital timing-recovery circuit uses this phase difference to provide an initial coarse alignment between the read signal and the sample clock and reduces the overall alignment-acquisition time.
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