An input-buffered multipoint switch having input channels and output channels includes multilevel request buffers (122, 124, 126, and 128), a data path multiplexer (130), and a scheduler (132). The switch has a distinct multilevel request buffer associated with each input channel and each request buffer has multiple request registers (160, 162, 164, and 166) of a different request buffer priority. The request registers (160, 162, 164, and 166) store data cell transfer requests that have been assigned quality of service (QoS) priorities, where the QoS priorities are related to packet source, destination, and/or application type. The multilevel request registers (160, 162, 164, and 166) are linked in parallel to the scheduler (132) to allow arbitration among requests of different input channels and different request buffer priority levels. The preferred arbitration process involves generating QoS priority-specific masks that reflect the output channels required by higher QoS priority requests and arbitrating (256) among requests of the same QoS priority in QoS priority-specific multilevel schedulers. Sorting requests by QoS priority allows the switch to schedule a high throughput of packets while adhering to QoS requirements.