In some embodiments, the invention includes an interconnect system (50) having a single ended driver (54) and single ended hysteretic receiver (58). A single ended interconnect (66) is coupled between the single ended driver and single ended receiver. In other embodiments (figure 4), the invention involves an interconnect system including interconnects (66A, 66B), single ended drivers (54A, 54B), and single ended hysteretic receivers (58A, 58B) connected to respective ones of the interconnects. The single ended drivers receive respective data-in signals (Din(0), Din(1)) and an enable signal (Enable) and wherein the drivers transmit interconnect signals on the interconnects when the enable signal is asserted. In yet other embodiments (140), the invention includes an interconnect system having interconnects (66A, 66B), quasi-static drivers (142A, 142B) and receivers (150A, 150B) connected to respective ones of the interconnects, the quasi-static drivers receive a clock signal (CLK) and respective data-in signals (Din(0), Din(1)), and wherein the interconnect signals are pre-discharged when the clock signal changes from a first to a second state, and wherein when the clock signal is in the first state, the interconnect signals are related to the data-in signals. In still other embodiments, the invention includes a pseudo differential interconnect system (90) and an interconnect system with a dual rail driver (190).