A QAM demodulator comprises a timing synchroniser 7 whose output is supplied via an adaptive equaliser 8 to a carrier synchroniser 9, all of which are controlled by a controller 6. The timing synchroniser 7 resamples the incoming signal in the digital domain with a sampling period which, during an acquisition mode, sweeps between limit values at different rates. The controller 6 begins an acquisition cycle at the highest rate and monotonically lowers the sweep rate until timing lock is achieved. The sampling rate is then fixed at the correct value. Similarly, the controller 6 sweeps the local oscillator of a phase locked loop in the carrier synchroniser 9 initially at a highest rate and at progressively lower rates until the carrier synchroniser 9 locks to the phase of the incoming signal.