发明公开
EP1160698A3 Method and device for multi-interval chebyshev collocation for efficient high accuracy circuit simulation
审中-公开
用于高度精确的电路仿真多个间隔搭配的方法和装置
- 专利标题： Method and device for multi-interval chebyshev collocation for efficient high accuracy circuit simulation
- 专利标题（中）： 用于高度精确的电路仿真多个间隔搭配的方法和装置
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申请号： EP01113710.6申请日： 2001-06-05
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公开(公告)号： EP1160698A3公开(公告)日： 2004-10-20
- 发明人: Yang, Baolin , Phillips, Joel
- 申请人： Cadence Design Systems, Inc.
- 申请人地址： 2655 Seely Road, Building 5 San Jose California 95134 US
- 专利权人： Cadence Design Systems, Inc.
- 当前专利权人： Cadence Design Systems, Inc.
- 当前专利权人地址： 2655 Seely Road, Building 5 San Jose California 95134 US
- 代理机构： Fiener, Josef
- 优先权： US208724P 20000602; US873988 20010601
- 主分类号： G06F17/50
- IPC分类号： G06F17/50
摘要：
A method and apparatus are provided for solving a set of differential-algebraic equation arising in a circuit simulation is provided. A collocation method is applied to each differential-algebraic equation to discretize the set of differential-algebraic equations. A solution to the set of differential-algebraic equations based on the discretized differential-algebraic equation is then formed.
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