发明公开
- 专利标题： Phase locked loop having a reduced lock time
- 专利标题（中）： 具有降低锁定时间锁相环
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申请号： EP01306946.3申请日： 2001-08-15
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公开(公告)号： EP1182780A3公开(公告)日： 2003-05-02
- 发明人: Sutton, Brian P.
- 申请人： Tektronix, Inc.
- 申请人地址： 14200 S.W. Karl Braun Drive, P.O. Box 500 Beaverton, OR 97077 US
- 专利权人： Tektronix, Inc.
- 当前专利权人： Tektronix, Inc.
- 当前专利权人地址： 14200 S.W. Karl Braun Drive, P.O. Box 500 Beaverton, OR 97077 US
- 代理机构： Molyneaux, Martyn William
- 优先权： US645212 20000824
- 主分类号： H03L7/189
- IPC分类号： H03L7/189
摘要：
A reduced lock time phase locked loop has a speed up circuit with an operational amplifier (24) to amplify a differential voltage across a filter resistor (R1) of an RC noise filter, the RC noise filter (R1,C) coupling a coarse tune voltage to a VCO (12). The amplified differential voltage is applied to the bases of a pair of opposite polarity transistors (Q1,Q2), the emitters of the transistors being coupled to a filter capacitor (C) in the RC noise filter for rapid charging/discharging. Alternatively the amplified differential voltage is applied to a pair of parallel, opposite polarity diodes (D1,D2) coupled to the filter capacitor for rapid charging/discharging.
公开/授权文献
- EP1182780B1 Phase locked loop having a reduced lock time 公开/授权日：2005-11-09
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