An oversampling circuit and a digital/analog converter which have small circuit scales and the component costs of which are reduced. The oversampling circuit comprises four D flip-flops (10-1 to 10-4), four multipliers (12-1 to 12-4), three adders (14-1 to 14-3), and two integrating circuits (16-1, 16-2). Input data is fed sequentially to the four D flip-flops and held therein. The multipliers multiply the data held in the respective D flip-flops by different multiplicators in the first half and second half of one clock period, and the multiplication results are added by the three adders. Furthermore, two digital integrating operations corresponding to the sum are carried out by means of the two integrating circuit.