发明公开
EP1191602A3 Method of forming trench MOS device and termination structure
审中-公开
Methode zur Herstellung eines MOS-Bauelementes mit Graben und Randabschlussstruktur
- 专利标题: Method of forming trench MOS device and termination structure
- 专利标题(中): Methode zur Herstellung eines MOS-Bauelementes mit Graben und Randabschlussstruktur
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申请号: EP01122745.1申请日: 2001-09-21
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公开(公告)号: EP1191602A3公开(公告)日: 2004-12-29
- 发明人: Chih-Wei, Hsu , Chung-Min, Liu , Ming-Che, Kao , Ming-Jinn, Tsai , Pu-Ju, Kung
- 申请人: GENERAL SEMICONDUCTOR, Inc.
- 申请人地址: 10 Melville Park Road Melville, NY 11747-3113 US
- 专利权人: GENERAL SEMICONDUCTOR, Inc.
- 当前专利权人: GENERAL SEMICONDUCTOR, Inc.
- 当前专利权人地址: 10 Melville Park Road Melville, NY 11747-3113 US
- 代理机构: Bohnenberger, Johannes, Dr.
- 优先权: US668906 20000922
- 主分类号: H01L29/78
- IPC分类号: H01L29/78 ; H01L21/336 ; H01L21/331 ; H01L29/861 ; H01L29/739 ; H01L29/06
摘要:
A method for fabricating trench MOS devices and termination structure simultaneously is disclosed. The MOS devices can be Schottky diode, IGBT or DMOS depending on the semiconductor substrate prepared. The method comprises following steps: firstly, forming a plurality of first trenches for forming the trench MOS devices in an active region, and a second trench for forming the termination structure. Thereafter, a thermal oxidation process to form a gate oxide on all areas is performed. Then, the first trenches and the second trench are refilled with a first conductive material. An etching back is carried out to remove excess first conductive material so as to form spacer in the second trench and to fill the first trenches only. Next, the gate oxide layer is removed. For IGBT or DMOS device, an extra thermal oxidation and an etching step are required to form inter-conductive oxide layer whereas for Schottky diode, these two steps are skipped. Thereafter, a termination structure oxide layer is formed through deposition, lithographic process and etching. After backside unnecessary layers removal, a sputtering metal layers deposition, lithographic process and etching step are successively performed to form the first electrode with a desired ended location and the second electrode on both side of semiconductor substrate.
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