发明公开

  • 专利标题: VOLTAGE LIMITING BIAS CIRCUIT FOR REDUCTION OF HOT ELECTRON DEGRADATION EFFECTS IN MOS CASCODE CIRCUITS
  • 专利标题(中): 限压偏倚减少MOS的降解效果级联
  • 申请号: EP01923205.7
    申请日: 2001-04-05
  • 公开(公告)号: EP1195004A2
    公开(公告)日: 2002-04-10
  • 发明人: GRADZKI, Pawel, M.
  • 申请人: Cadence Design Systems, Inc.
  • 申请人地址: 2655 Seely Avenue San Jose, CA 95134 US
  • 专利权人: Cadence Design Systems, Inc.
  • 当前专利权人: Cadence Design Systems, Inc.
  • 当前专利权人地址: 2655 Seely Avenue San Jose, CA 95134 US
  • 代理机构: Dendorfer, Claus, Dr.
  • 优先权: US545321 20000406
  • 国际公布: WO0182470 20011101
  • 主分类号: H03F1/22
  • IPC分类号: H03F1/22
VOLTAGE LIMITING BIAS CIRCUIT FOR REDUCTION OF HOT ELECTRON DEGRADATION EFFECTS IN MOS CASCODE CIRCUITS
摘要:
MOS Cascode amplifier circuit including a voltage limiting bias circuit of additional transistors acting as a series voltage-limiting device between the MOS cascode amplifier circuit output node and the drain node of the upper-most cascode connected transistors when the MOS cascode amplifier circuit output voltage is at its maximum value. The drain-source voltage excursion peak on the sensitive cascode transistor is limited to a value below a pre-selected critical voltage, Vcrt. The additional transistors are connected by internal adjacent source-drain nodes as a sequencial chain with gates biased at respective fixed voltages. The number of additional transistors are selected to limit the peak drain-source voltage excursion on the sensitive transistor under operating conditions.
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