发明公开
EP1215730A4 SiC WAFER, SiC SEMICONDUCTOR DEVICE AND PRODUCTION METHOD OF SiC WAFER
有权
SiC-HALBLEITERCHEIBE,SiC-HALBLEITERBAUELEMENT SOWIE HERSTELLUNGSVERFAHRENFÜREINE SiC-HALBLEITERCHEIBE
- 专利标题: SiC WAFER, SiC SEMICONDUCTOR DEVICE AND PRODUCTION METHOD OF SiC WAFER
- 专利标题(中): SiC-HALBLEITERCHEIBE,SiC-HALBLEITERBAUELEMENT SOWIE HERSTELLUNGSVERFAHRENFÜREINE SiC-HALBLEITERCHEIBE
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申请号: EP00956966申请日: 2000-09-06
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公开(公告)号: EP1215730A4公开(公告)日: 2003-02-05
- 发明人: SHIOMI HIROMU , KIMOTO TSUNENOBU , MATSUNAMI HIROYUKI
- 申请人: SIXON INC , KANSAI ELECTRIC POWER C C INC , MITSUBISHI CORP , SUMITOMO ELECTRIC INDUSTRIES
- 专利权人: SIXON INC,KANSAI ELECTRIC POWER C C INC,MITSUBISHI CORP,SUMITOMO ELECTRIC INDUSTRIES
- 当前专利权人: SIXON INC,KANSAI ELECTRIC POWER C C INC,MITSUBISHI CORP,SUMITOMO ELECTRIC INDUSTRIES
- 优先权: JP25315299 1999-09-07
- 主分类号: C30B23/00
- IPC分类号: C30B23/00 ; C30B23/02 ; H01L21/04 ; H01L29/04 ; H01L29/24 ; H01L29/78 ; H01L29/16 ; C30B25/00 ; C30B25/02 ; C30B25/20 ; C30B29/36 ; H01L29/47
摘要:
A SiC wafer comprises a 4H polytype SiC substrate 2 in which the crystal plane orientation is substantially ä03-38ü, and a buffer layer 4 composed of SiC formed over this SiC substrate 2. The ä03-38ü plane forms an angle of approximately 35 DEG with respect to the axial direction in which micropipes and so forth extend, so micropipes and so forth are eliminated at the crystal sides, and do not go through to an active layer 6 on the buffer layer 4. Lattice mismatching between the SiC substrate 2 and the active layer 6 is suppressed by the buffer layer 4. Furthermore, anisotropy in the electron mobility is low because a 4H polytype is used. Therefore, it is possible to obtain a SiC wafer and a SiC semiconductor device with which there is little anisotropy in the electron mobility, and strain caused by lattice mismatching can be lessened, as well as a method for manufacturing these.
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