An A/D converter array (13) has A/D converters (210) each corresponding to each row of photodetector elements (120) of a photodetector array (11). An image-processing unit (14) includes a plurality of processing circuits (400) for high-speed image processing. A signal converter (17) combines the output signal from the A/D converter array (13) and the output signal from the image-processing unit (14). Under control of a control circuit (15) and a signal conversion controller (19), the signal converter (17) downconverts the combined signal at a frame rate suitable for the display of monitor (18), particularly at important timing.