An integrated cache memory circuit is provided comprising a tag RAM, a comparator and a data RAM. Each of the tag RAM and the date RAM have an array of memory cells and plural sense amplifiers. Each memory cell of the RAMs is connected via a respective bit line to one of the plural sense amplifiers. The sense amplifiers of the tag RAM have respective outputs coupled to a first input of the comparator. The comparator having a second input for address information and an output for selectively enabling data output from sense amplifiers of the data RAM. The memory cells of the tag RAM are arranged to have a higher current drive than the memory cells of the data RAM.