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EP1333446A2 Circuit and method for testing a ferroelectric memory device 审中-公开
Schaltung und Verfahren zum Testen eines Ferroelektrischen Speichers

Circuit and method for testing a ferroelectric memory device
Abstract:
A test circuit and method are disclosed for testing memory cells of a ferroelectric memory device having an array of ferroelectric memory cells. The test circuitry is coupled to the bit lines, for selectively determining the voltage levels appearing on the bit lines based on a measured current level and providing externally to the ferroelectric memory device an electrical signal representative of the sensed voltage levels. In this way, ferroelectric memory cells exhibiting degraded performance may be identified.
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