A fill pattern for a semiconductor device such as a memory cell. The memory cell includes a plurality of first topographic structures comprising conductive lead lines (305, 306, 307) deposited on a semiconductor substrate, and a plurality of second topographic structures comprising fill patterns (350) such that the top surfaces of the second topographic Structures are generally coplanar with the top surfaces of the plurality of first topographic Structures. The plurality of first and second topographic Structures are arranged in a generally repeating array on the substrate. A planarization layer (320) is deposited on top of the substrate such that it fills the space between the plurality of first and second topographic structures, with its top surface generally coplanar with that of the top surfaces of the first and second topographic structures.