发明公开
EP1517369A2 Method of manufacturing wafer level chip size package
审中-公开
Verfahren zur Herstellung eines“Chip-size-package”auf Waferebene
- 专利标题： Method of manufacturing wafer level chip size package
- 专利标题（中）： Verfahren zur Herstellung eines“Chip-size-package”auf Waferebene
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申请号： EP04255574.8申请日： 2004-09-15
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公开(公告)号： EP1517369A2公开(公告)日： 2005-03-23
- 发明人: Murakami, Takehiko c/o Minami Co. Ltd.
- 申请人： Minami Co. Ltd.
- 申请人地址： 38-32 Minamimachi 5-chome Fuchu-shi, Tokyo JP
- 专利权人： Minami Co. Ltd.
- 当前专利权人： Minami Co. Ltd.
- 当前专利权人地址： 38-32 Minamimachi 5-chome Fuchu-shi, Tokyo JP
- 代理机构： Neill, Alastair William
- 优先权： JP2003325938 20030918
- 主分类号： H01L23/31
- IPC分类号： H01L23/31 ; H01L23/485
摘要：
To widely improve an entire manufacturing efficiency by efficiently forming a thermal stress relaxing post, an insulating layer and a solder bump, arewiringcircuit (3) is formedonawafer (1) byplating, a thermal stress relaxing post (4) made of a conductive material such as a solder or the like is formed on the rewiring circuit (3), an insulating layer (6) made of a polyimide or the like is formed in the periphery of the rewiring circuit (3) and the thermal stress relaxing post (4) except a top surface of the thermal stress relaxing post (4), a solder bump (7) is formed on the thermal stress relaxing post (4), and the thermal stress relaxing post (4), the insulating layer (6) and the solder bump (7) are formed by screen printing.
公开/授权文献
- EP1517369A3 Method of manufacturing wafer level chip size package 公开/授权日：2010-10-13
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