A voltage down-converter system, with a stand-by mode and an active mode, for a memory device with the following components. A charge node (68) is configured to receive a charge. A first transistor (54) has a first gate and the first transistor is configured to supply a load current to the memory device. A first switch (58) is coupled to the charge node and the first gate, the first switch being configured to apply the charge in the charge node to the first gate during transition from stand-by to active modes. A second transistor (66) is coupled to the first gate and configured to bias the first transistor to an inactive state during stand-by mode. A second switch (64) is coupled to the first gate and the second transistor, the second switch being configured to apply a voltage difference at the second transistor to the first gate during the stand-by mode.