发明公开
EP1554726A2 FREQUENCY AND PHASE CONTROL APPARATUS AND MAXIMUM LIKELIHOOD DECODER
审中-公开
DEVICE FOR频率和相位控制和最大似然解码器
- 专利标题: FREQUENCY AND PHASE CONTROL APPARATUS AND MAXIMUM LIKELIHOOD DECODER
- 专利标题(中): DEVICE FOR频率和相位控制和最大似然解码器
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申请号: EP03756705.4申请日: 2003-10-20
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公开(公告)号: EP1554726A2公开(公告)日: 2005-07-20
- 发明人: MIYASHITA, Harumitsu , NAKAJIMA, Takeshi , KIMURA, Naohiro
- 申请人: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
- 申请人地址: 1006, Oaza-Kadoma Kadoma-shi,Osaka 571-8501 JP
- 专利权人: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
- 当前专利权人: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
- 当前专利权人地址: 1006, Oaza-Kadoma Kadoma-shi,Osaka 571-8501 JP
- 代理机构: Pautex Schneider, Nicole
- 优先权: JP2002308229 20021023
- 国际公布: WO2004038719 20040506
- 主分类号: G11B20/10
- IPC分类号: G11B20/10
摘要:
A frequency and phase control apparatus (100) includes an analog/digital conversion section (62) for converting a reproduction signal into a multiple bit digital (64) signal based on a clock signal (63); a maximum likelihood decoding section (4) for converting the multiple bit digital signal into a binary signal (66); a pattern detection section (50) for detecting a pattern of the binary signal; and a determination section (11) for determining whether or not the multiple bit digital signal and the clock signal are in synchronization with each other based on the detection result. When the determination result of the determination section indicates that the multiple bit digital signal and the clock signal are in synchronization with each other, the maximum likelihood decoding section generates a binary signal based on a first state transition rule (fig.12); otherwise, the maximum likelihood decoding section generates a binary signal based on a second state transition rule (fig.13).
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