发明公开
- 专利标题: HDTV downconversion system
- 专利标题(中): AbwärtsumwandlungssystemfürHDTV-signale
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申请号: EP05016820.2申请日: 1998-03-11
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公开(公告)号: EP1628479A2公开(公告)日: 2006-02-22
- 发明人: Kim, Hee-Yong , Naimpally, Saiprasad , Meyer, Edwin Robert , Sita, Richard , Phillips, Larry , Egawa, Ren
- 申请人: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
- 申请人地址: 1006, Oaza Kadoma Kadoma-shi, Osaka 571-8501 JP
- 专利权人: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
- 当前专利权人: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
- 当前专利权人地址: 1006, Oaza Kadoma Kadoma-shi, Osaka 571-8501 JP
- 代理机构: Schwabe - Sandmair - Marx
- 优先权: US40517P 19970312
- 主分类号: H04N7/01
- IPC分类号: H04N7/01
摘要:
The invention concerns a digital video signal conversion system for decoding and reformatting a baseband encoded digital video signal having a first video display format during a first time interval and a second video display format during a second time interval to produce a decoded video signal suitable for display in a single predetermined video display format, each video display format having an aspect ratio and a resolution, the system comprising:
a digital video signal decoder (171, 172, 174) including:
an input terminal coupled to receive the encoded digital video signal having the first video display format during the first time interval and the second video display format during the second time interval, the first video display format being different from the second video display format and both the first and second video display formats being different from the predetermined video display format;
data retrieval circuitry (209) which extracts from the encoded digital video signal data identifying the first video display format during the first time interval and second video display format during the second time interval; and
signal processing circuitry (212, 214, 216, 218, 230, 232, 282) which decodes the encoded digital video signal to produce a decoded video signal, the signal processing circuitry (212, 214, 216, 218, 230, 232, 282) including a frequency domain filter (216) having first and second cutoff frequencies during the first and second time intervals, respectively, and a down sampling processor (232) to process the filtered digital video signal according to a first down conversion process during the first time interval and to a second down conversion process during the second time interval;
a polyphase filter (282), responsive to a filter control signal, for selecting a coefficient set from among a plurality of coefficient sets, responsive to a downsampling ratio between the decoded video signal and the single predetermined video display format, the polyphase filter down-sampling the decoded video signal using respectively different coefficient sets during the first and second intervals, respectively, to produce data representing an image having the video display format; and
a controller (1150), coupled to receive the identifying data which identifies the extracted first and second video display format, the controller (1150) producing control signals for the digital video signal decoder (171, 172, 174) and for the polyphase filter (282) during the first and second time intervals which cause the decoder and the polyphase filter (282) to convert the encoded digital video signal corresponding to the extracted first and second display formats into the output video signal having the single predetermined video display format during the first and second time intervals.
a digital video signal decoder (171, 172, 174) including:
an input terminal coupled to receive the encoded digital video signal having the first video display format during the first time interval and the second video display format during the second time interval, the first video display format being different from the second video display format and both the first and second video display formats being different from the predetermined video display format;
data retrieval circuitry (209) which extracts from the encoded digital video signal data identifying the first video display format during the first time interval and second video display format during the second time interval; and
signal processing circuitry (212, 214, 216, 218, 230, 232, 282) which decodes the encoded digital video signal to produce a decoded video signal, the signal processing circuitry (212, 214, 216, 218, 230, 232, 282) including a frequency domain filter (216) having first and second cutoff frequencies during the first and second time intervals, respectively, and a down sampling processor (232) to process the filtered digital video signal according to a first down conversion process during the first time interval and to a second down conversion process during the second time interval;
a polyphase filter (282), responsive to a filter control signal, for selecting a coefficient set from among a plurality of coefficient sets, responsive to a downsampling ratio between the decoded video signal and the single predetermined video display format, the polyphase filter down-sampling the decoded video signal using respectively different coefficient sets during the first and second intervals, respectively, to produce data representing an image having the video display format; and
a controller (1150), coupled to receive the identifying data which identifies the extracted first and second video display format, the controller (1150) producing control signals for the digital video signal decoder (171, 172, 174) and for the polyphase filter (282) during the first and second time intervals which cause the decoder and the polyphase filter (282) to convert the encoded digital video signal corresponding to the extracted first and second display formats into the output video signal having the single predetermined video display format during the first and second time intervals.
公开/授权文献
- EP1628479A3 HDTV downconversion system 公开/授权日:2007-09-05
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