发明公开
EP1654661A2 AN APPARATUS AND METHOD FOR MEMORY ENCRYPTION WITH REDUCED DECRYPTION LATENCY 审中-公开
装置和方法进行加密以减少的时延解码的存储器

  • 专利标题: AN APPARATUS AND METHOD FOR MEMORY ENCRYPTION WITH REDUCED DECRYPTION LATENCY
  • 专利标题(中): 装置和方法进行加密以减少的时延解码的存储器
  • 申请号: EP04754772.4
    申请日: 2004-06-09
  • 公开(公告)号: EP1654661A2
    公开(公告)日: 2006-05-10
  • 发明人: ROZAS, CarlosGRAUNKE, Gary
  • 申请人: INTEL CORPORATION
  • 申请人地址: 2200 Mission College Boulevard Santa Clara, CA 95052 US
  • 专利权人: INTEL CORPORATION
  • 当前专利权人: INTEL CORPORATION
  • 当前专利权人地址: 2200 Mission College Boulevard Santa Clara, CA 95052 US
  • 代理机构: Beresford, Keith Denis Lewis
  • 优先权: US603680 20030625
  • 国际公布: WO2005006197 20050120
  • 主分类号: G06F12/14
  • IPC分类号: G06F12/14 G06F1/00
AN APPARATUS AND METHOD FOR MEMORY ENCRYPTION WITH REDUCED DECRYPTION LATENCY
摘要:
A method and apparatus for memory encryption with reduced decryption latency. In one embodiment, the method includes reading an encrypted data block from memory. During reading of the encrypted data block, a keystream used to encrypt the data block is regenerated according to one or more stored criteria of the encrypted data block. Once the encrypted data block is read, the encrypted data block is decrypted using the regenerated keystream. Accordingly, in one embodiment, encryption of either random access memory (RAM) or disk memory is performed. A keystream is regenerated during data retrieval such that once the data is received, the data may be decrypted using a single clock operation. As a result, memory encryption is performed without exacerbating memory latency between the processor and memory.
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